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ADS中文版使用指南（CodeWarrior使用教程）
ADS中文版使用指南（CodeWarrior使用教程）-ADS use the Chinese version of the Guide (CodeWarrior directory)
- 2022-02-28 15:46:45下载
- 积分：1
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原作者：
这是我学数据结构编写的算法，我把他整理出来，都是基本算法，供大家学习。我使用c++面向对象形式编写，各种算法都封装在各自的类里，如果想增加功能，在...
原作者：
这是我学数据结构编写的算法，我把他整理出来，都是基本算法，供大家学习。我使用c++面向对象形式编写，各种算法都封装在各自的类里，如果想增加功能，在相应的类里增加函数即可。我对树和图的构造也做了一些人性化设计，输入更加形象化，你可能看不懂，没关系漫漫来。各种类都使用模版设计，可以对各种数据类型操作（整形，字符，浮点）-Original author: This is my data structure of the algorithm, I regard him finishing out of the basic algorithm is for them to learn. I use c++ Prepared in the form of object-oriented, all kinds of algorithms are encapsulated in their respective classes, if you want to increase functionality, in the corresponding category can increase function. I map the structure of trees and have done some human design, the importation of more figurative, you may not understand, does not matter for long. Use various types of templates designed to operate on various data types (plastic, characters, floating-point)
- 2022-03-05 05:16:56下载
- 积分：1
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Computer Vision
计算机视觉--马颂德 比较不错的教材，拿出来大家分享-Computer Vision- Ma Songde relatively good materials out to share with
- 2022-01-25 15:54:31下载
- 积分：1
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一本很好的入门书，对常见的知识搜索engnine的天网…
a very good introductory book about common knowledge of search engnine by SkyNet Team in PKU
- 2022-04-27 05:17:31下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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vc++设计宝典教程4
vc++设计宝典教程4-vc Design Guide 4
- 2023-05-16 04:10:02下载
- 积分：1
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may tinh bo tui hjbjjjhgjgjhgvhcvnn
may tinh bo tui hjbjjjhgjgjhgvhcv-may tinh bo tui hjbjjjhgjgjhgvhcvnn
- 2022-08-02 20:30:02下载
- 积分：1
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Autolisp 是AutoCad 与外部软件的接口程序
Autolisp 是AutoCad 与外部软件的接口程序-Autolisp is AutoCad with external software interface program
- 2023-07-15 04:40:03下载
- 积分：1
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IBM_written examination__gather
IBM_笔试_精华集合。想进IBM的一定要看-IBM_written examination__gather
- 2022-02-01 01:04:56下载
- 积分：1
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source operating indicators Chain
指针链表操作源码-source operating indicators Chain
- 2022-05-21 20:50:14下载
- 积分：1
