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警卫控制系统,主要 控制 电梯系统 ,通过422通讯格式完成与电梯系统之间的 通讯协议。...
警卫控制系统,主要 控制 电梯系统 ,通过422通讯格式完成与电梯系统之间的 通讯协议。-Security control system, the main control elevator systems, through to complete the 422 communication format, communication protocol between the elevator system.
- 2022-01-25 18:31:08下载
- 积分:1
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dac9747
主要完成ADI公司的DAC(数字-模拟转换器)AD9747的SPI接口及寄存器配置(Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of)
- 2014-06-03 11:00:43下载
- 积分:1
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基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码,其功能主要有:时间设置,时间显示,跑表,分频,日期设置,日期显示等...
基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码,其功能主要有:时间设置,时间显示,跑表,分频,日期设置,日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
- 2022-02-12 09:36:35下载
- 积分:1
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Ultrasound
软件环境:TI的zstack协议栈
硬件:CC2530无线单片机
功能:利用超声波模块实现测距(该模块型号:HC-SR04 在淘宝上非常常见) 可测2厘米到3米距离(Software environment: TI' s zstack protocol stack hardware: CC2530 wireless microcontroller features: use of ultrasonic ranging module (the module Model: HC-SR04 on Taobao very common) can be measured 2 cm to 3 meters)
- 2020-12-28 23:39:02下载
- 积分:1
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Construction-and-Experimental-Evaluations-of-User
Construction and Experimental Evaluations of User-Centered Power
- 2011-11-29 08:35:34下载
- 积分:1
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用VHDL语言实现CPLD(EPM240T100C5组成)串口接收程序
利用VHDL实现CPLD(EPM240T100C5)的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure
- 2022-05-20 12:04:11下载
- 积分:1
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vivado 从此开始配套资料
说明: vivado入门使用介绍,初学者入门学习(vivado Instructional pdf)
- 2020-07-04 18:00:01下载
- 积分:1
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To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分:1
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m序列生成VHDL代码
伪随机m序列VHDL代码,生成多项式为1+x+x^7 (203),包括代码文件.vhd和模块文件.bsf以及仿真波形,可直接添加到工程中使用。
- 2023-02-01 13:50:03下载
- 积分:1
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ethernet_udp_ep4c_ok_final
用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)
- 2015-04-27 01:15:36下载
- 积分:1