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VGA_Display(FPGA)
在FPGA开发平台上,通过按键控制一个弹球小游戏。输出VGA显示信号输送到显示器上显示(On the FPGA development platform button control of a pinball game. VGA output signal is supplied to the display displayed on the display)
- 2017-05-02 10:59:42下载
- 积分:1
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__keyBoard
vhdl编写的4X4键盘扫描程序,可以有效的消除抖动,并且提供蜂鸣器输出。(VHDL prepared 4X4 keyboard scanner, you can effectively eliminate jitter and provide buzzer output.)
- 2007-10-24 09:11:11下载
- 积分:1
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各大IT、软件、硬件公司薪资
本文档内容是各大公司的薪资,各位可以了解一下,绝对真实,具体到个位数。
- 2023-04-05 21:30:03下载
- 积分:1
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ISCAS`89基准电路下载(包括Verilog和VHDL格式)
SCAS `89 基准电路下载,包括Verilog和VHDL格式。verilog格式30个文件:包括S1238、S13207等;(SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;)
- 2021-01-02 15:58:56下载
- 积分:1
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8B10B
以太网PHY层中的组成部分 8B10B编码器(Part of the Ethernet PHY layer in 8B10B encoder
)
- 2021-01-27 09:18:42下载
- 积分:1
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Digital-clock
数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能:1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能(Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function)
- 2013-07-18 18:11:44下载
- 积分:1
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DecimationFilterDesignforDDCandImplementingItwithF
本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB
滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性(This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design)
- 2008-04-14 11:02:00下载
- 积分:1
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verilogPWM波的设计
verilogPWM波的设计,属于数字电子技术实验入门的资料
- 2023-02-19 19:15:04下载
- 积分:1
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veriloghdllicheng135li
Verilog的应用例程,包含了基本的硬件编程,加法器,触发器(Application of Verilog routines, including the basic hardware programming, adders, flip-flop)
- 2010-12-14 20:38:03下载
- 积分:1
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clock18div
Clock Divider, divfactor of 18
- 2015-03-24 18:04:49下载
- 积分:1