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FPGA2-DSP2-EDMA
例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
- 2020-12-04 16:09:24下载
- 积分：1
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Altera Corporation for DE2 development board of the TV demonstration
用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration
- 2022-03-26 12:20:58下载
- 积分：1
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UART_prj_ViHDL
vhdl project at sbu uni in iran
uart
- 2010-05-08 16:18:37下载
- 积分：1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分：1
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my_test_rw_pack9
基于Verilog HDL的SDRAM控制器。
实验条件：
工具：Quartus II 6.0 ,SignalTap II
FPGA：Altera Cyclone EP1C12Q240C8N
SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclone EP1C12Q240C8N
SDRAM: HY57V283220T-6)
- 2013-01-31 11:13:26下载
- 积分：1
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zidong-shouhuoji
用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)
- 2014-01-05 20:42:49下载
- 积分：1
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采用VHDL编写的七段数码管显示程序
采用VHDL编写的七段数码管显示程序-prepared using VHDL paragraph 107 of the procedures Digital Display
- 2022-07-28 16:14:18下载
- 积分：1
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常见的几种电机的特征与控制方法
常见的几种电机的特征与控制方法-Several common characteristics of the motor and control method
- 2023-03-02 10:15:03下载
- 积分：1
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ADPCM
说明： APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)
- 2009-08-22 10:07:03下载
- 积分：1
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AD
说明： 基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)
- 2019-07-30 14:00:57下载
- 积分：1
