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selfmade UART HDL code
用veriloghdl编写的自制UART。在modelsim下
- 2022-02-06 08:15:25下载
- 积分:1
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DTMB
能够完美产生数字地面电视(DTMB)的信源的程序。帧头模式为模式一。信道可选择,信号加入频偏,延时,后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分:1
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pipeline_booth_mult_16
用流水线的方法实现16位乘法器,运算速度快,消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
- 2020-09-29 18:17:44下载
- 积分:1
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Nexys-4-DDR-XADC
Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)
- 2018-12-07 15:33:22下载
- 积分:1
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SASX
说明: Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
- 2020-06-24 11:40:02下载
- 积分:1
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Writing-Testbenches
这是一本FPGA仿真验证的经典丛书,可以从中学习到如何编写系统的testbench,也可以是IC设计中FPGA原型验证编写系统及testbench的经典书籍。((Kluwer) Writing Testbenches Functional Verification of HDL Models.pdf)
- 2015-06-20 13:39:06下载
- 积分:1
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20190717 - Copy
this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分:1
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electricwatch
用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)
- 2010-05-07 17:11:53下载
- 积分:1
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基于FPGA的QPSK调制解调
基于FPGA的QPSK调制解调,正交调制输出,解调包括NCO,载波同步,定时同步。modelsim仿真实测通过。
- 2022-02-12 13:01:39下载
- 积分:1
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verilog 万能流水灯
FPGA流水灯程序 适合新手学习FPGA,板子用的是Altera,只是其中一种方法,简单的会了,以后就不成问题了
- 2023-04-15 10:55:03下载
- 积分:1