登录
首页 » VHDL » 数字频率计VHDL程序

数字频率计VHDL程序

于 2022-05-21 发布 文件大小:1.66 kB
0 142
下载积分: 2 下载次数: 1

代码说明:

数字频率计VHDL程序 --文件名:plj.vhd。 --功能:频率计。具有4位显示,能自动根据7位十进制计数的结果,自动选择有效数据的 --高4位进行动态显示。小数点表示是千位,即KHz。-Digital Cymometer VHDL procedures- File name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • alarm
    闹钟设计,VHDL,源代码。闹钟设计,VHDL,源代码。(Alarm clock design, VHDL, the source code.)
    2011-05-23 18:30:29下载
    积分:1
  • youmui_v20
    ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.
    2017-09-01 20:51:26下载
    积分:1
  • vga_graph_st
    该程序用vhdl编写的vga显示的小游戏,到时屏幕上会显示一个小球,一根棒子,一面墙,棒子可以通过按键控制来移动。而小球在不停的运动,遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)
    2013-05-18 21:01:23下载
    积分:1
  • du to fpga 4*4 keyscan verilog
    基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog
    2022-01-25 20:49:28下载
    积分:1
  • 2022-12-14 10:50:03下载
    积分:1
  • Multi_function
    01 线性调频信号的卷积功能测试(匹配) 02 LFM一维距离像 03 MATLAB联合FPGA仿真输入/输出功能测试 04 解速度模糊 05 扩展目标检测(01 LFM Test function of "conv" 02 LFM Range 03 MATLAB and FPGA 04 resovle speed resolution 05 Extended moving target)
    2013-05-03 15:53:43下载
    积分:1
  • This procedure for the Verilog control ADC all procedures can be applied to test
    此程序为Verilog控制ADC的全部程序,已检验可以应用-This procedure for the Verilog control ADC all procedures can be applied to test
    2023-04-20 20:25:03下载
    积分:1
  • This is a simple routine FPGA is mainly based on FPGA
    这是一个FPGA的简单例程,主要是基于FPGA的232串口通信的例程-This is a simple routine FPGA is mainly based on FPGA-232 serial communication routines
    2022-03-06 20:54:43下载
    积分:1
  • FPGA based implementation of a SDR
    FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
    2022-12-18 09:05:03下载
    积分:1
  • Dec_mul
    时间同步后即可确定每帧数据的起始位置,这样就能完整的截取下每一帧。但是,数据中还带有频偏信息。在常规的通信系统中,多普勒很小仅仅会带来很小的频偏,但是在大多普勒的情况下,频偏将非常大,20马赫的速度将会带来将近34K的频偏。因此,如何很好的纠正频偏即为本系统的难点。 OFDM中,我们将大于子载波间隔倍数的频偏称为整数倍频偏,而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔,频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想,由于硬件资源限制,我们将在接收端做64点FFT,即相当于将频域划分为64份,我们将小于 的频偏称为小数倍频偏,将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
    2013-12-26 18:00:24下载
    积分:1
  • 696516资源总数
  • 106415会员总数
  • 3今日下载