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Cadence-Allegro-PCB-SI
利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)
- 2013-08-06 22:17:46下载
- 积分:1
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38LCD
LCD图形显示代码,已调试过,可以运行成功(LCD graphics display code has been debugged, you can run successfully)
- 2012-08-22 23:08:39下载
- 积分:1
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8位相 加乘法器,具有高速,占用资源较少的优点
8位相 加乘法器,具有高速,占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
- 2023-05-06 21:10:02下载
- 积分:1
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First_conv
mimo—ofdm线性卷积,实现输入的800位宽的数据同两个序列的卷积(Mimo- ofdm linear convolution
800 bits wide input data with the convolution of two sequences
)
- 2013-03-30 09:18:56下载
- 积分:1
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GUI
1)选择一个语音信号作为分析对象,或录制一段语音信号; 2)对语音信号进行采样,画出采样前后语音信号的时域波形和频谱图; 3)利用MATLAB中的随机函数产生噪声加入到语音信号中,使语音信号被污染,然后进行频谱分析; 4)设计用于处理该语音信号的数字滤波器,给出滤波器的性能指标,画出滤波器的频率响应; 5)对被噪声污染的语音信号进行滤波,画出滤波前后信号的时域波形和频谱,并对滤波前后的信号进行比较和分析; 6)回放各步骤的语音信号,给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)
- 2021-03-18 17:29:19下载
- 积分:1
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TCL2543
基于FPGA的TLC2543控制器,采用状态进行控制ADC进行转换(The TLC2543 controller based on FPGA, using state control of ADC conversion)
- 2020-11-18 15:59:39下载
- 积分:1
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divider
用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)
- 2020-11-19 11:39:37下载
- 积分:1
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Tun2CNk2
FPGA实现DSP的Verilog 示例(FPGA realization of DSP-Verilog Example)
- 2008-05-05 17:08:19下载
- 积分:1
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inverter chain
说明: 基于HSPICE实现的反相器链,并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)
- 2020-04-21 12:55:52下载
- 积分:1
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hammingaTB
Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.
- 2013-11-06 15:45:02下载
- 积分:1