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带LDN的的同步的预置数端子，并且带CLR的异步清零端
带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
- 2022-02-22 00:30:35下载
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上海大学 Verilog PPT 适合初学者看 推荐
上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners
- 2022-04-19 13:38:15下载
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计数器的VHDL语言程序实现1
VHDL语言编写的计数器程序，实现1到9999计数，并动态扫描显示，带清零和暂停功能，课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
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VHDLcoding
本文件时VHDL的各种编写规范，有助于开发者在平时养成好的编码习惯(This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime)
- 2009-11-20 11:44:58下载
- 积分：1
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一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。...
一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
- 2023-06-07 08:05:03下载
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Advanced-FPGA-Design
高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2021-04-01 11:09:08下载
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E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
- 2023-06-23 08:30:04下载
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VHDL语言100例详解
说明： VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。(VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.)
- 2005-09-04 17:15:21下载
- 积分：1
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uart
一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)
- 2013-07-25 11:43:34下载
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适用于满足I2C协议的flash读/写操作程序，只需要设置要读/写的字节数，就可以直接使用！...
适用于满足I2C协议的flash读/写操作程序，只需要设置要读/写的字节数，就可以直接使用！-Applicable to meet the I2C protocol flash read/write operations, only need to set to read/write number of bytes can be used directly!
- 2023-04-08 02:50:03下载
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