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This document is formatted UltraEdit document describes some of the original Ult...
这个文件中是UltraEdit的一些格式化文件说明
由于原来的 UltraEdit 不支持 HDL 语言的格式化显示,把文件解压得到的 wordfile.txt替换其安装目录下的 wordfile.txt 文件即可-This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its installation directory under the document can wordfile.txt
- 2022-09-16 02:20:04下载
- 积分:1
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rscode
R S编 解 码 实 现 代 码
verilog语言(RS CODE AND ENCODE)
- 2013-05-19 16:19:55下载
- 积分:1
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qam_64
Verilog语言下QAM调制的DDS实现(The QAM Modulation DDS achieve)
- 2021-02-20 11:59:43下载
- 积分:1
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VerilogHDL_DC_Motor_control
采用Verilog HDL语言编写的直流电动机控制系统,主要完成直流电动机的速度控制,典型的三闭环(位置、转速和电流反馈)直流电机控制系统,对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)
- 2008-01-10 23:34:29下载
- 积分:1
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histogram_new
Verilog语言描述,统计图片的像素值直方图(Verilog,Pictures of the pixel value histogram statistics)
- 2021-03-04 17:39:31下载
- 积分:1
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代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心...
代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping
- 2022-04-13 03:11:13下载
- 积分:1
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Traffic_RYG
说明: 交通灯的控制,分主干道和从路交通灯,主路优先,正常情况下,绿灯60s,红灯30S,黄灯5S(Traffic light control)
- 2020-06-21 06:40:02下载
- 积分:1
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dspafpga
dsp与fpga通信的verilog程序,强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)
- 2020-12-04 15:59:23下载
- 积分:1
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audio_verilog
AUDIO音频模块AN831的录音及播放FPGA代码,测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)
- 2020-09-12 09:27:58下载
- 积分:1
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内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...
内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
- 2022-08-11 02:50:00下载
- 积分:1