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关于寄存器重命名register reallocation,VHDL
关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
- 2022-02-09 20:31:31下载
- 积分：1
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ch3ex
部分组合逻辑数字电路的VHDL代码，包含必要的功能描述(Some combinational logic digital circuits VHDL code, containing the necessary functional description)
- 2009-01-31 21:26:34下载
- 积分：1
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RISC-V-Reader-Chinese-v2p1
说明： RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
- 2020-07-01 23:00:02下载
- 积分：1
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用于sopc builder添加组件用的ps/2
键盘 ipcore
用于sopc builder添加组件用的ps/2
键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore
- 2022-03-12 14:54:04下载
- 积分：1
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Copy-of-DIGITAL-VLSI-DESIGN
a manual for design implementation of fpga and ASIC using verilog
- 2012-09-04 17:34:58下载
- 积分：1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
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22_deadlock
说明： 本例的源描述超过了演示版限制的300行,
如果您需要对其进行编译与模拟,请与北京理工大学
ASIC研究所联系,获取Talent系统的完全版本.
联系方法:
电话:010-68912434
(The source described in this case than the demo version of the 300 line limit, if you need to be compiled with the simulation, please contact ASIC Institute of Beijing Institute of Technology to obtain the complete version of Talent system. Contact: Tel :010-68912434)
- 2008-09-09 18:11:58下载
- 积分：1
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ps2
使用verliog实现ps2键盘接口的驱动，通过altera cyclone 第四代验证通过(Use verliog implement ps2 keyboard interface driven by a fourth-generation verified by altera cyclone)
- 2015-12-17 16:28:38下载
- 积分：1
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asynchronous serial communication port of the FPGA, function (1) serial data rec...
异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
- 2023-06-21 16:25:03下载
- 积分：1
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ahb_sramc_vtb
ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)
- 2020-08-25 20:48:15下载
- 积分：1
