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serial_communication
说明： 串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)
- 2006-04-06 09:38:19下载
- 积分：1
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1_ADDER
说明： 第1例到第6例的源描述都是从第8例的程序包中
提取出来的,不能单独编译,这些例子的编译与
模拟请参考第8例.(Example No. 1 to the first six cases are the source described in Example 8 from the first package to extract it and can not be a separate compiler, which compiler and simulation examples please refer to the first eight cases.)
- 2008-09-09 18:00:16下载
- 积分：1
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九九乘法器
基于对ROM的编写，在quartusII上实现九九乘法器的实现，在试验箱的四个数码管上分别显示乘数，被乘数，积
- 2022-02-03 19:00:51下载
- 积分：1
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ug835-vivado-tcl-commands
说明： Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
- 2020-10-26 22:50:00下载
- 积分：1
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利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块...
利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module
- 2022-02-25 00:52:03下载
- 积分：1
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verilog
说明： i2c module，有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)
- 2020-10-26 08:27:29下载
- 积分：1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分：1
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sht30
温湿度传感器sht30驱动，系统时钟为125M可读出温湿度。(sht30 driver,sysclk=125MHZ)
- 2020-09-28 17:07:44下载
- 积分：1
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这是使用VHDL编写的交通灯程序,供大家交流学习
这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning
- 2022-04-29 16:41:55下载
- 积分：1
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用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。...
用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- 2022-04-19 09:59:57下载
- 积分：1
