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This is a very good book c
这是一本很好的c++书-This is a very good book c
- 2022-01-25 21:17:44下载
- 积分：1
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通信中LDPC编码的源程序
通信中LDPC编码的源程序-LDPC coded communication source
- 2022-03-03 10:54:04下载
- 积分：1
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认证教材，不要错过下载机会，是你通过sun的认证不可不看的教材！...
认证教材，不要错过下载机会，是你通过sun的认证不可不看的教材！-teaching certification should not miss the opportunity to download, you have passed the certification sun can not see the teaching!
- 2022-01-22 06:52:40下载
- 积分：1
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命令，命令
,at commands ,at commands -,at commands,at commands,at commands,at commands
- 2023-04-29 15:20:03下载
- 积分：1
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swing程序开发指南，具有很高的实用价值，有借鉴意义
swing程序开发指南，具有很高的实用价值，有借鉴意义-swing Programming Guide, has high practical value, a reference
- 2022-10-12 14:45:04下载
- 积分：1
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随着光伏系统MPPT
Photovoltaic system with mppt
- 2022-11-04 03:25:04下载
- 积分：1
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objects with EPC network will be following the Internet after another killer app...
EPC与物联网将是继互联网之后的又一个杀手级的应用 该书为中国电子标签委员会出的最有权威性的书-objects with EPC network will be following the Internet after another killer application for the electronic book labels Committee of the most authoritative book
- 2023-08-06 13:15:03下载
- 积分：1
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winsock入门，还可以，作为winsock入门不错，可以参考。
winsock入门，还可以，作为winsock入门不错，可以参考。-winsock entry, you can also, as the winsock entry Yes, you can refer to.
- 2022-01-21 23:08:17下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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C primer plus (第五版)本书源代码及习题答案
C primer plus (第五版)本书源代码及习题答案
- 2022-02-02 12:29:22下载
- 积分：1
