rs232 verilog code inclouding of TRX and testbench.

代码说明：

rs232 verilog code inclouding of TRX and testbench. This zip file contains the following folders: verilog_source  -- Source Verilog files:  uart.v   -- top level file  txmit.v  -- transmit portion of uart  rcvr.v   -- receive portion of uart -- Source Verilog files:  txmit_tf.v -- testbench for transmit portion of uart  rcvr_tf.v  -- testbench for receive portion of uart