-
log10(x)
Fixed-point base-2 logarithm (DW_log2)
// Computes the base-2 logarithm of a fixed point value in the
// range [1,2).
- 2014-09-11 19:58:10下载
- 积分:1
-
基于FPGA的CPU核及其虚拟平台的设计与实现
基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
- 2022-08-08 02:35:45下载
- 积分:1
-
DA(AD768)
AD768产生锯齿波的源码,DA转化的最基本操作。(AD768 sawtooth source code, the basic operation of DA conversion.)
- 2014-03-19 09:39:54下载
- 积分:1
-
SD-Host-Controller-master
说明: sd卡的verilog代码,包含一些sd卡例程(SD card Verilog code, including some SD card routines)
- 2021-04-29 13:48:42下载
- 积分:1
-
RS_CC_ENC
OFDM系统新型CC编解码的verilogHDL设计,与RS编码级联,经测试误码率性能提高(OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement)
- 2020-12-31 10:58:59下载
- 积分:1
-
example16-dac7512-sina-wave-ok
VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)
- 2014-12-08 14:02:34下载
- 积分:1
-
用VHDL语言将二进制数据转换成十进制数据,并将十进制的每一个位分离出来单独存放。使用状态机实现,程序简单,仿真效果很理想,占用可编程器件的资源较少。...
用VHDL语言将二进制数据转换成十进制数据,并将十进制的每一个位分离出来单独存放。使用状态机实现,程序简单,仿真效果很理想,占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.
- 2023-03-27 15:30:04下载
- 积分:1
-
VHDL 2008 A reference book on VHDL
VHDL 2008 A reference book on VHDL-VHDL 2008 A reference book on VHDL
- 2022-02-07 15:24:00下载
- 积分:1
-
XC3S700_UART_Test
红色飓风3S700AN开发板UART测试例程(Red Hurricane 3S700AN development board UART test code)
- 2013-07-12 00:34:31下载
- 积分:1
-
《Verilog HDL 程序设计教程》3
《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3
- 2023-02-08 02:25:03下载
- 积分:1