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利 用 来 vhdl 设 计 p cm的 实 现
利 用 来 vhdl 设 计 p cm的 实 现-Vhdl design used for the realization of p cm
- 2023-06-01 20:05:03下载
- 积分:1
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led5604
5604FPGA驱动,能显示数字(5604里面为4个595)(5604 FPGA driver, able to display digital (5604 contains 4 595))
- 2020-06-19 18:00:01下载
- 积分:1
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PAL_VGA
基于FPGA的PAL_VGA转换器的实现.pdf(FPGA-based PAL_VGA converter implementation)
- 2009-03-17 14:13:36下载
- 积分:1
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俄罗斯方块(Xilinx版)
说明: 用verilog语言开发俄罗斯方块小游戏(Developing Tetris game with Verilog language)
- 2020-11-27 08:47:38下载
- 积分:1
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TFT_CTRL_800_480_16bit
说明: 文件用于驱动TFT屏,分辨率800*400,平台为quartus13,芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
- 2019-04-12 09:22:29下载
- 积分:1
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h264_intp
图形图像H264插值算法,应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)
- 2021-05-14 18:30:02下载
- 积分:1
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DDR_interface
高速DDR存储器数据接口设计实例.
1. 将文件拷入硬盘
2. 产生DQS模块
3. 产生DQ模块
4. 产生PLL模块
5. 拷贝以上步骤生成的文件到子目录【Project】中
6. 打开子目录【Project】中的DataPath.qpf工程,设计顶层模块
7. 编译并查看编译结果
(High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see)
- 2009-04-27 11:52:56下载
- 积分:1
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29_ad9226_test
说明: 用Verilog编写ad_9866的相应程序,在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)
- 2019-06-24 16:43:27下载
- 积分:1
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基本逻辑门电路的设计方法,或门的VHDL的设计让你更容易步入VHDL的设计氛围中,简单的或门编制...
基本逻辑门电路的设计方法,或门的VHDL的设计让你更容易步入VHDL的设计氛围中,简单的或门编制-Basic logic gate circuit design methods, or the door of the VHDL design allows you to more easily into the VHDL design environment, the simple OR gate preparation
- 2022-01-30 19:12:35下载
- 积分:1
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URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器,也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号...
URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器,也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列,以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号,以决定继续进行那些数据运算,数据单元要产生输出信号,数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.
- 2022-03-24 14:43:33下载
- 积分:1