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pll
fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:01下载
- 积分：1
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EEPROM_at25320a
Commponent for drivering EEPROM memory AT25320 from Avalon bus.
- 2013-11-22 00:04:04下载
- 积分：1
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FPGA锁相环实验
说明： FPGA锁相环实验：
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分：1
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基于basys3的推箱子游戏
基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)
- 2021-03-12 13:09:25下载
- 积分：1
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DDS_DAC_Output
说明： 本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分：1
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usbFPGAconnect
该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。(The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program)
- 2021-04-08 15:19:00下载
- 积分：1
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led_test
在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA
)
- 2013-08-13 08:55:45下载
- 积分：1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分：1
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MapCG
cpu与GPU协同计算一个同时支持GPU与CPU的MapReduce框架实现(cpu and GPU collaborative computing)
- 2014-12-04 23:06:54下载
- 积分：1
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sqrt_pipeline
说明： Matlab - to hdl code for square root
- 2020-06-17 12:20:02下载
- 积分：1
