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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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usb控制器,有VHDL实现的,还有C++的源码,可以编译
usb控制器,有VHDL实现的,还有C++的源码,可以编译-usb controller, there is the realization of VHDL, as well as C++ source code can be compiled
- 2022-03-31 17:48:55下载
- 积分:1
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信号完整性,设计FPGA的基础
信号完整性,设计FPGA的基础-signal integrity, design based FPGA
- 2022-09-25 03:05:03下载
- 积分:1
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贪吃蛇文件
用游戏把子上下左右控制蛇的方向,寻找吃的东西,每吃一口就能得到一定的积分,而且蛇的身子会越吃越长,身子越长玩的难度就越大,不能碰墙,不能咬到自己的身体,更不能咬自己的尾巴,等到了一定的分数,就能过关,然后继续玩下一关。
- 2022-04-13 02:07:58下载
- 积分:1
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Subway_VHDL
模拟地铁自动售票机选票、付款、取票、找零等功能,包含软件仿真和硬件响应,可供仿真测试和FPGA验证。(Analog subway ticket vending machine ballots, payment, tickets, give change and other features, including software simulation and hardware response for simulation and FPGA verification test.)
- 2016-03-14 10:44:14下载
- 积分:1
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一种新的FPGA实现AES-128采用降低残留素数的S盒
应用背景在本文中,我们提出了一种新的FPGAAES的S盒的利用高性能的实现减少素数的残留。这个该设计在Xilinx Virtex-5实现xc5vlx50 FPGA器件。目的是使用一种新的基于查找表的条目集渣盒素数。减少残留素S盒数量增加了更多的混乱,AES的整个过程算法,使其更复杂,并提供进一步抵抗攻击。我们的实现达到了3.09 Gbps的吞吐量,共采用了1745片一个Virtex-5 FPGA。关键技术AES的应用减少了素数剩余的设计基于S盒是用VHDL语言实现一个Xilinx Virtex-5 xc5vlx50(包:ffg676,速度等级:3)使用FPGA设计工具ISE 9.2i。表4FPGA实现结果表明AES减少残留的素数的S盒。它介绍了Xilinx公司的FPGA器件选择的目标,加密吞吐量实现,定时报告和整体设备利用率。
- 2022-02-02 18:37:31下载
- 积分:1
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万能频率器,可以修改其中的参数,可是实现任意的分频!很方便!...
万能频率器,可以修改其中的参数,可是实现任意的分频!很方便!-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
- 2022-01-26 04:43:16下载
- 积分:1
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vhdl,序列信号发生器,发出11101010,可更改为任意序列
vhdl,序列信号发生器,发出11101010,可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of
- 2023-08-12 03:05:03下载
- 积分:1
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dianzhen
如果需要用verilog设计一项比较简单的功能,那么这个浅显易懂的程序能让你很快明白点阵的设计方法,尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)
- 2014-01-16 16:13:53下载
- 积分:1
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TOFED_TB_1
A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?
- 2014-11-08 06:58:55下载
- 积分:1