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RS_Encoder
具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)
- 2012-08-06 11:52:37下载
- 积分：1
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基于EDA技术设计4位十进制数字频率计的系统方案
基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer
- 2022-03-21 02:07:27下载
- 积分：1
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VHDL语言设计；功能描述：键盘扫描，不包含去抖电路
VHDL语言设计；功能描述：键盘扫描，不包含去抖电路-VHDL language design Function description: the keyboard scanning, does not contain a circuit debounced
- 2022-08-26 08:21:49下载
- 积分：1
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volt_mea_disp
本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)
- 2013-07-26 00:58:35下载
- 积分：1
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verilog实现的1024位的大数模逆算法，引入RAM作为数据通道
verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
- 2022-12-18 20:35:03下载
- 积分：1
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rough22
采用倍频及1/3、1/12倍频绘制的路面不平度频谱图（自编）(Using octave and 1/3, 1/12 octave drawn road roughness spectrum (self))
- 2013-09-10 16:50:13下载
- 积分：1
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93 std
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
- 2022-02-25 16:35:00下载
- 积分：1
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Viterbi译码器的编解码器的设计
用Verilog实现
Viterbi译码器的编解码器的设计
用Verilog实现-Viterbi decoder。Verilog
- 2022-09-18 21:30:03下载
- 积分：1
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单片机与FPGA串行通信的源代码，非常实用哦
单片机与FPGA串行通信的源代码，非常实用哦-Single-chip serial communication with the FPGA source code, very useful Oh
- 2022-01-31 08:59:52下载
- 积分：1
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sph-original-codes
SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分：1
