登录
首页 » VHDL » FPGA的仿真实例,Verilog代码编写,过程详尽,代码易懂。第四个文档...

FPGA的仿真实例,Verilog代码编写,过程详尽,代码易懂。第四个文档...

于 2022-05-31 发布 文件大小:32.26 kB
0 67
下载积分: 2 下载次数: 1

代码说明:

FPGA的仿真实例,Verilog代码编写,过程详尽,代码易懂。第四个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The fourth document

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • dac9747
    主要完成ADI公司的DAC(数字-模拟转换器)AD9747的SPI接口及寄存器配置(Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of)
    2014-06-03 11:00:43下载
    积分:1
  • verilog编写的alu模块
    verilog编写的alu模块-Verilog modules prepared by the ALU
    2022-11-20 13:50:03下载
    积分:1
  • huffman
    huffman transform in vhdl language
    2013-08-26 13:17:15下载
    积分:1
  • seven_persons
    自己写的7人表决器的verilog程序,实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)
    2013-08-10 07:15:06下载
    积分:1
  • 由VHDL 语言实现的DA0832器利用的是QUARTUES环境已经得到验证
    由VHDL 语言实现的DA0832器利用的是QUARTUES环境已经得到验证-By the VHDL language uses the DA0832 is QUARTUES environment has been tested
    2023-02-01 00:40:03下载
    积分:1
  • USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including...
    USB 1.1 PHY的代码,systemc语言 USB 1.1 PHY的代码,systemc语言,包括基于systemc语言的testbench ,和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
    2022-04-12 00:51:05下载
    积分:1
  • SDRAM
    verilog编写的SDRAM实验,有串口调试助手和相关资料!!!!!!!!!!!!!!!!!!!!!(Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!)
    2014-09-13 11:24:46下载
    积分:1
  • This program is Verlog language program, using QUARTUS6.0 preparation, program i...
    本程序为Verlog语言程序,采用QUARTUS6.0编写,程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
    2022-02-10 16:51:45下载
    积分:1
  • 系统设计
    说明:  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
    2020-06-21 01:20:08下载
    积分:1
  • multiply
    由verilog编写的乘法器,通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)
    2008-12-30 20:51:33下载
    积分:1
  • 696524资源总数
  • 103930会员总数
  • 47今日下载