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resolutionquartusII
用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)
- 2021-05-14 18:30:02下载
- 积分：1
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FIFO
Simulation and Synthesis Techniques for Asynchronous
FIFO Design
- 2013-08-27 16:07:08下载
- 积分：1
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Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can...
用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-10 06:00:42下载
- 积分：1
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GgmsskModulatM
GMSK的调制解调，理理想信道，画出其功率谱。
(GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)
- 2020-07-02 02:00:02下载
- 积分：1
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41_eth_ddr3_lcd
说明： “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)
- 2021-03-21 00:33:00下载
- 积分：1
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color_bar
彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)
- 2020-06-22 06:20:01下载
- 积分：1
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CRC_restored
mpeg-2 crcr32计算的代码，采用verilog编写，验证通过(mpeg-2 crcr32 caculate)
- 2011-09-25 10:54:08下载
- 积分：1
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cpu_design
FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)
- 2020-12-03 13:09:25下载
- 积分：1
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Modulation
产生长度为100的随机二进制序列
发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱
相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特）
接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特）
采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特）
(Produce random binary sequence of length 100
The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum
Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits)
The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits)
DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits)
DPSK and delay)
- 2020-12-14 08:19:14下载
- 积分：1
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DongHo
design a clock using KIT DE1
- 2014-09-19 04:46:23下载
- 积分：1
