-
基于FPGA的JPEG图像压缩芯片设计
基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
- 2022-01-28 02:00:46下载
- 积分:1
-
singlecycle_mips
single cycle mips design by verilog.
- 2020-09-07 19:48:02下载
- 积分:1
-
华为经典FPGA设计全套入门技巧
说明: 华为FPGA设计全套资料,学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)
- 2019-04-02 13:54:48下载
- 积分:1
-
8. For the key to enter a password lock, assuming that reset after the seven lam...
8对于输入密码锁的键,假设重置后七个灯显示" 0",并且使用sw1、sw2、sw3 3,只需按任意sw1、sw2、sw3,将使七个灯显示值相加" 1
- 2022-07-16 11:58:58下载
- 积分:1
-
0720_03_AD_uart
说明: 基于fpga的verilog实现ad及uart,并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)
- 2019-01-21 20:52:46下载
- 积分:1
-
篮球24秒可控计时器设计
用VHDL语言设计篮球24秒可控计时器功能说明:1.具有24秒计时、显示功能; 2.设置外部按键,完成清零、暂停、恢复控制; 3.24秒倒计时,时间间隔为1s; 4.时间到后发出报警信号,并在3s后解除。
- 2022-05-28 22:06:17下载
- 积分:1
-
fft64
verilog hdl 编写的64点fft代码,适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分:1
-
8051参考设计,和其他免费知识产权在8051相比,相对整个D。
8051参考设计,与其他8051的免费IP相比,文档相对较全,Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
- 2023-01-19 15:30:04下载
- 积分:1
-
SystemVerilog_For_Design_Springer_2nd_Ed_2006
SystemVerilog For Design (Springer-2nd_Ed-2006)
- 2009-10-08 02:57:28下载
- 积分:1
-
2D4N_com
2维4节点的UEL单元,嵌入UMAT,采用j2 mises屈服准则(2d4nodes uel elements, with umat codes, and j2 mises flow rule)
- 2014-06-04 20:43:21下载
- 积分:1