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realization of the project document ARM system CPLD logic, external resources ha...
该工程文件实现ARM系统中CPLD的逻辑工作，起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function
- 2022-02-05 23:05:52下载
- 积分：1
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8051MCU in the FPGA to achieve the source code, using VHDL language
8051MCU在FPGA上实现的源代码，用VHDL语言编写-8051MCU in the FPGA to achieve the source code, using VHDL language
- 2022-02-22 06:28:53下载
- 积分：1
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Of PCM
对PCM编码的多路复用与解复用程序，VerilogHDL源程序-Of PCM-encoded multiplexing and demultiplexing process, VerilogHDL source
- 2022-02-05 07:01:51下载
- 积分：1
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Lossless_Compression_Method_for_Bayer_Image_and_FP
描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)
- 2010-08-31 12:24:49下载
- 积分：1
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myuart
使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分：1
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gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分：1
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1024point-fft--using-verilog-hdl
1024点快速傅里叶变换，使用verilog hdl硬件描述语言(1024point FFT，using verilog hdl)
- 2013-03-09 10:54:42下载
- 积分：1
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VHDL implement serial port, it can communicate with pc, it can accept and send m...
用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
- 2022-02-11 22:49:32下载
- 积分：1
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snake_VHDL
基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)
- 2020-11-06 09:49:50下载
- 积分：1
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使用CORDIC实现三角函数计算，使用VHDL语言实现
利用cordic实现三角函数的计算，用vhdl实现-use cordic achieve trigonometry calculations, using achieve vhdl
- 2022-01-20 22:30:42下载
- 积分：1
