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快速输入输出互连规范物理层。
快速IO互连规范物理层。
- 2022-03-29 06:06:06下载
- 积分：1
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国内各大卫视（卫星电视台）节目信号收集，基于sohu网络
国内各大卫视（卫星电视台）节目信号收集，基于sohu网络-The leading TV (satellite TV) program signals collection, web-based sohu
- 2022-07-19 15:51:53下载
- 积分：1
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ARX secondary development and change layer
ARX二次开发，改变图层-ARX secondary development and change layer
- 2022-12-27 13:45:02下载
- 积分：1
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一个全屏幕的俄罗斯方块的游戏 .rar
一个全屏幕的俄罗斯方块的游戏 .rar-a full screen of Tetris game. Rar
- 2022-09-02 11:00:04下载
- 积分：1
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介绍c或c++的嵌入式系统编程的书籍，内容详细
介绍c或c++的嵌入式系统编程的书籍，内容详细-Introduction c or c++ for embedded systems programming books, detailed
- 2023-02-16 14:20:03下载
- 积分：1
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ARM应用系统开发详解.rar, 对想了解ARM的人来说，是不错的文档...
ARM应用系统开发详解.rar, 对想了解ARM的人来说，是不错的文档-Detailed ARM Application Development. Rar, for those who would like to know the ARM is a good document
- 2023-06-09 14:45:04下载
- 积分：1
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软件开发的文档标准，
软件开发的文档标准，-Software development, documentation standards,
- 2022-08-16 05:54:14下载
- 积分：1
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GBK，gb3212 Unicode详细、GBK编码，gb3212 Unicode编码的细节…
GBK，GB3212 Unicode编码问题详解,GBK，GB3212 Unicode编码问题详解-GBK, GB3212 Unicode encoding of detailed, GBK, GB3212 Unicode encoding of detailed
- 2022-04-10 03:12:13下载
- 积分：1
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本书详细介绍了c++的技术，为中高级程序员使用，是一本内容丰富，很有深度的国际标准书籍...
本书详细介绍了c++的技术，为中高级程序员使用，是一本内容丰富，很有深度的国际标准书籍-Described in detail in this book c++ of the technology, the use of senior programmers, are rich in content and a very deep book of international standards
- 2022-05-31 09:11:18下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
