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verilog写的数字频率计的控制模块,对程序进行控制
verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
- 2022-02-04 00:52:27下载
- 积分:1
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作者:新舜唐日期:2008
--author: Suntion Tang
--date: 2008-6-7
-- two warning
--modify: By Suntion Tang at 2008-6-14
--description: 顶层文件,由于此系统简单,
-- 且底层文件不多,故放弃原理图描述,采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description
- 2022-04-23 09:59:29下载
- 积分:1
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stopwatch-based-on-VHDL
基于VHDL的电子秒表的设计,使用VHDL语言描述一个秒表电路,利用QuantusII软件进行源程序设计,编译,仿真,最后形成下载文件下载至装有FPGA芯片的实验箱,进行硬件测试,要求实现秒表功能。(Design of electronic stopwatch based on VHDL)
- 2013-11-27 15:42:41下载
- 积分:1
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led_prj
spartan 3E和verilog HDL的初学者极好的教材,本程序可直接下载到spartan实验板上运行。(Spartan 3E and Verilog HDL beginners excellent materials, the program can be downloaded directly to the spartan experimental board run.)
- 2013-04-17 13:35:42下载
- 积分:1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分:1
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eeprom
I2C EEPROM 存取源碼, 通用ATMEL(I2C EEPROM read/write)
- 2012-09-19 19:59:12下载
- 积分:1
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testbench.sv
RS 编码和解码Verilog Code, 实现了RS(544,514)的编码和译码;(-RS Coding and Decoding Verilog code, implement RS(544,514))
- 2016-09-25 16:05:54下载
- 积分:1
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本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读....
本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读.
- 2023-03-07 07:25:03下载
- 积分:1
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dct
基于FPGA的图像压缩算法程序,自己写的,可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)
- 2011-10-23 00:54:17下载
- 积分:1
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altremote_update_cyclone5
altera remote updata cyclone5 平台例程,无nios核版本(altera remote updata cyclone5 platform routine
do not use nios)
- 2021-04-23 17:38:47下载
- 积分:1