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Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分：1
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AD_sample
AD采集模块,设计模块采集AD5270的输出数据(AD Collection module
Design module to collect the output data of AD5270
)
- 2020-11-18 16:19:39下载
- 积分：1
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MD5
哈希算法FPGA实现代码，采用MD5算法，并给出了仿真波形。(MD5 hashing algorithm for FPGA implementation code)
- 2020-07-03 00:40:02下载
- 积分：1
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FPGA_homewrk4
设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述，给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)
- 2018-05-07 17:54:12下载
- 积分：1
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一个8位CISC结构的精简CPU，2还提供了编译器
一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
- 2022-02-28 11:37:41下载
- 积分：1
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EPM570并串转换器
基于CPLD器件EPM570，用VHDL语言编写的并串转换器代码，用于实现并行代码到串行代码的转换
- 2022-07-13 17:44:24下载
- 积分：1
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PIDcontrolbook2
PID CONTROLLER HELPING BOOK
- 2009-03-26 18:18:04下载
- 积分：1
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auk_sdsdi
说明： 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能(for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on)
- 2020-11-11 12:39:44下载
- 积分：1
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verilog
数字信号除了的FPGA实现的Verilog源代码，之前发过一份是VHDL，各有所需吧，需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
)
- 2012-02-25 15:06:35下载
- 积分：1
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4x4 electronic locks central control system. Six input control.
4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.
- 2022-02-10 10:06:12下载
- 积分：1
