-
通用存储器VHDL代码库,The Free IP Project VHDL Free
通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library.
-generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
- 2022-05-26 21:22:15下载
- 积分：1
-
Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
Qutuas II v7.1的key_gen 对sp1无效
这就是个v7.1 sp1的key_gen
-Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
- 2023-07-28 18:25:02下载
- 积分：1
-
gmii_tx_mac
实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)
- 2013-08-08 15:24:43下载
- 积分：1
-
div_fru
介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)
- 2010-06-17 21:52:55下载
- 积分：1
-
SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分：1
-
jiaozhijiejiaozhi
VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)
- 2020-07-17 15:08:49下载
- 积分：1
-
add16
designing of 16 bit adder using 4 bit adder using verilog code
- 2012-09-10 14:40:32下载
- 积分：1
-
通过VHDL语言的例子，乒乓球运动的FPGA原型样机（2章）是
应用背景FPGA原型的VHDL例子提供一系列清晰，易于遵循的快速代码开发模板；大量的实际例子来说明和强化的概念和设计技术；现实可实施的项目和测试在Xilinx原型板；深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-08-13 14:19:44下载
- 积分：1
-
ALOHA
this program is a simulation for Aloha
- 2012-11-13 11:38:10下载
- 积分：1
-
snake
贪吃蛇程序，用verilog实现，可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)
- 2016-01-16 21:11:14下载
- 积分：1
