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关于DNS,FTP,WWW,DHTP服务器的架设
关于DNS,FTP,WWW,DHTP服务器的架设-on DNS, FTP, WWW, the erection DHTP server
- 2022-06-03 04:59:36下载
- 积分：1
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根据拓扑的吞吐量、丢包和延迟数据计算网络的总体损害
根据拓扑的吞吐量、丢包和延迟数据计算网络的总体损害-According to topology throughput, packet loss and latency data of the network" s overall damage to
- 2022-10-08 19:00:03下载
- 积分：1
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动态规划的相关资料，dp主要是寻找递归关系，这里面有很多类型的dp资料便于学习...
动态规划的相关资料，dp主要是寻找递归关系，这里面有很多类型的dp资料便于学习-Dynamic programming related information, dp is mainly to find a recursive relationship, and there are many types of information to facilitate learning of dp
- 2023-03-20 23:40:03下载
- 积分：1
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模式编程，很好的学习材料。用c++编写的非常的不错
模式编程，很好的学习材料。用c++编写的非常的不错-Mode of programming, good learning materials. With c++ Prepared very well
- 2022-10-19 01:45:04下载
- 积分：1
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学习C语言必备的好书
学习C语言必备的好书-C language learning books required
- 2022-03-17 21:07:06下载
- 积分：1
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《编程之美》随书源代码（第二部分），第2章 数字之魅 ――数字中的技巧...
《编程之美》随书源代码（第二部分），第2章 数字之魅 ――数字中的技巧
-" The Beauty of Programming," With the source code for the book (Part II)
- 2022-05-11 02:22:33下载
- 积分：1
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关于传输线具体原理和实际用途的阐述．包括公式推导．
关于传输线具体原理和实际用途的阐述．包括公式推导．-On the transmission line theory and the actual use of specific elaboration. Including the derived formula.
- 2022-11-02 14:55:03下载
- 积分：1
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New windowAPI Daquan
新编windowAPI大全-New windowAPI Daquan
- 2022-05-23 12:48:16下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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Simple procedures should not be allowed entry time for your station to station t...
简单入门程序不要让站长把时间为您修正站长把时间都花费在-Simple procedures should not be allowed entry time for your station to station to amend the time spent on
- 2023-04-03 10:20:04下载
- 积分：1
