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固定长度 32 位乘法器
32 位有符号乘法 33 周期中的，它可以轻松地提高到可变延迟乘数，可以计算出这个乘数。
- 2022-07-15 11:53:06下载
- 积分：1
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verilog111.rar
verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦(verilog things properly used it, it is an essential learners verilog things oh)
- 2007-05-20 10:23:46下载
- 积分：1
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xilinx平台DDR3设计教程之仿真篇_中文版教程
DRD3在Xlinix平台上的设计教程以及仿真(DRD3 design tutorial and Simulation on Xlinix platform)
- 2018-11-02 11:18:06下载
- 积分：1
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verilog fifo 代码
FIFO is a First-In-First-Out memory queue with control logic that manages
the read and write operations, generates status flags, and provides optional
handshake signals for interfacing with the user logic. It is often used to
control the flow of data between source and destination. FIFO can be
classified as synchronous or asynchronous depending on whether same clock
or different (asynchronous) clocks control the read and write operations. In
this project the objective is to design, verify and synthesize a synchronous
FIFO using binary coded read and write pointers to address the memory
array. FFIO full and empty flags are generated and passed on to source and
destination logics, respectively, to pre-empt any overflow or underflow of
data. In this way data integrity between source and destination is maintained.
The RTL description for the FIFO is
- 2022-05-22 08:44:13下载
- 积分：1
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adder4
四位加法器 数码管显示 组合电路 verilog(adder4 smg display combitional circuit verilog)
- 2013-02-28 09:56:46下载
- 积分：1
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I2C主实现用有限状态机
- 2022-03-18 18:02:01下载
- 积分：1
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uart_fifo
一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)
- 2021-04-25 22:38:46下载
- 积分：1
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shiyan5
应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)
- 2014-01-09 11:50:49下载
- 积分：1
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位同步实验程序参考bitsynchro
自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。(The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.)
- 2013-02-01 11:21:03下载
- 积分：1
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source
I2C MASTER DESIGNED by Verilog
- 2020-06-18 23:40:02下载
- 积分：1
