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实现了一个计算器应用程序,介绍了对话框添加菜单,高级按钮控件,高级编辑控件,对话框的扩展功能等应用。...
实现了一个计算器应用程序,介绍了对话框添加菜单,高级按钮控件,高级编辑控件,对话框的扩展功能等应用。-Realize a calculator application, introduction of the dialog box to add the menu, advanced button controls, a senior editor control extensions dialog applications.
- 2023-03-03 11:05:03下载
- 积分:1
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Java, a program to see if you know! From casual, it is hoped that useful,
Java的一个程序,看看就知道啦!
随便上传下,希望有用-Java, a program to see if you know! From casual, it is hoped that useful,
- 2022-01-26 19:53:36下载
- 积分:1
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C++ Primer的第三版结合了Stanley Lippman的实践经验和Josée Lajoie对于ANSI/ISO标准C++的深入理解...
C++ Primer的第三版结合了Stanley Lippman的实践经验和Josée Lajoie对于ANSI/ISO标准C++的深入理解-C Primer combination of the third edition of the Stanley Lippman had practical experience and Jose; for ANSI/ISO C standard in-depth understanding
- 2022-02-21 13:26:35下载
- 积分:1
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tuxedo中间件开发与配置
tuxedo中间件开发与配置-徐春金编著-tuxedo middleware development and deployment- edited by Xu Jin
- 2022-03-01 02:42:34下载
- 积分:1
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System will automatically delete the directory of debug and release, so please d...
System will automatically delete the directory of debug and release, so please do not put files on these two directory.
- 2023-08-25 15:45:05下载
- 积分:1
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C Primer and that the Chinese version of solutions. Part4
C++ Primer中文版及题解.part4-C Primer and that the Chinese version of solutions. Part4
- 2023-06-06 05:50:04下载
- 积分:1
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非常完整的关于C语言的电子版书籍!!非常值得一看!
非常完整的关于C语言的电子版书籍!!非常值得一看!-Very integrity of the C language on the electronic version of books! ! Very worth a visit!
- 2022-08-15 09:56:36下载
- 积分:1
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excel vba 编程指南 万伟峰撰写
excel vba 编程指南 万伟峰撰写-excel VBA programming guides written 10,000 weifeng
- 2022-07-23 13:27:55下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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Artificial Intelligence A Modern Approach Uncertainty.(2005
Artificial Intelligence A Modern Approach Uncertainty.(2005-2006 Winter Break Seminar)
By: Hyoseok Yoon
GIST U-VR Lab.
- 2023-07-20 18:35:04下载
- 积分:1