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dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
- 2023-03-22 17:40:04下载
- 积分：1
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FPGA
基于FPGA的频率相位可调DDS信号发生器-FPGA-based phase adjustable frequency DDS signal generator
- 2022-01-26 08:17:52下载
- 积分：1
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vhdl描述的显示代码 maxplus2开发环境
vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2
- 2022-07-25 04:14:57下载
- 积分：1
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FPGA design of a full set of frequency data, I hope all of you ah like useful
FPGA设计频率计全套资料，我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful
- 2023-01-04 19:10:03下载
- 积分：1
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cordic
基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。(Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.)
- 2013-12-20 17:22:38下载
- 积分：1
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VHDL实例这是我下载到的最好的VHDL实例，看完这些实例，可以使你有一个长足的进展...
VHDL实例这是我下载到的最好的VHDL实例，看完这些实例，可以使你有一个长足的进展-VHDL example
- 2022-08-10 14:33:29下载
- 积分：1
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pprobar
ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL
- 2013-12-09 04:26:42下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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verilog
说明： verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)
- 2010-03-18 12:11:18下载
- 积分：1
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SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程
SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程-SPI interface of the VHDL code can be achieved with SCM spi communication, complete works
- 2022-03-29 07:45:17下载
- 积分：1
