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Altera FPGA IP core of the source code for the use of Altera FPGA design to prov...
ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
- 2022-04-30 06:15:53下载
- 积分：1
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vga
VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。(the source code for driving VGA and displaying the images,the testbench was offered.)
- 2009-06-11 19:05:09下载
- 积分：1
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96x96数字复用/解复用SPI
96x96 Digital MUX/DEMUX via SPI
- 2023-08-24 02:45:04下载
- 积分：1
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matlab-gmsk
基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.(Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the simulation to verify the correctness of the phase calculation, is the cosine table generating quantitative and bin files, and using VHDL hardware description language logic based on the address of EPM7128.)
- 2020-12-19 10:39:10下载
- 积分：1
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mdct_latest.tar
mdct, it contains DOC,MATLAB,source,synthesis.
- 2009-12-11 14:15:39下载
- 积分：1
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MultHalfBand
基于Matlab的FPGA数字半带滤波器设计(Matlab-based FPGA digital half-band filter design)
- 2013-01-30 16:08:00下载
- 积分：1
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cordic-algorithm
codic algorithm,which is used to calculate triangular functions
- 2014-12-25 16:44:36下载
- 积分：1
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Xilinx 的DDR SDRAM控制器，用Verilog HDL描述
Xilinx 的DDR SDRAM控制器，用Verilog HDL描述-
A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA
- 2022-08-12 17:31:12下载
- 积分：1
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FIFO
fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)
- 2016-03-16 10:06:12下载
- 积分：1
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XADC
xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)
- 2021-03-29 15:19:10下载
- 积分：1
