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fpga_12864
这是基于Nios II的12864液晶点亮程序，包含汉字、字符等(This is a program which is based on Nios II ,its function is light the 12864 LCD that including Chinese characters, characters)
- 2012-07-02 17:28:21下载
- 积分：1
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This project features a full
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file.
Compression ratio is fixed for IMA-ADPCM, being 4:1.
PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
- 2022-07-25 20:05:07下载
- 积分：1
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GTX4
光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)
- 2016-06-28 14:06:40下载
- 积分：1
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vcp201_code是FPGA的源代码。
VCP201_CODE is a FPGA source code.
- 2023-06-03 07:10:03下载
- 积分：1
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2011-diansai-E
2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)
- 2012-02-23 10:11:07下载
- 积分：1
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yuqu
蜂鸣器音乐演奏，有ppt说明，及实例工程文件。(Music buzzer, a ppt notes, and examples of engineering documents.)
- 2020-12-27 20:09:02下载
- 积分：1
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generic_dpram
IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY
- 2013-09-30 19:03:40下载
- 积分：1
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High
高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard
- 2022-07-18 13:13:37下载
- 积分：1
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本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数
（N+0...
本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数
（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可
通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使
用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
- 2022-08-24 20:51:04下载
- 积分：1
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8.4-ADC0809-VHDL-control-program
基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)
- 2011-11-29 08:43:07下载
- 积分：1
