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Frecuencymeter
Frecuencymeter digital, clk frequency 10 MHZ, exhibition in 7 segments
- 2009-09-17 02:49:40下载
- 积分：1
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QPSK
用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。
(Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)
- 2011-01-24 17:46:44下载
- 积分：1
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cpu
说明： 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。(A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.)
- 2011-04-09 12:22:09下载
- 积分：1
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ripple adder
设计的结构是纹波进位加法器架构，但执行的操作是32位加法和32位减法
- 2023-07-02 19:50:04下载
- 积分：1
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基于FPGA的PCM编码器与解码器的设计
基于FPGA的PCM编码器与解码器的设计-about fpga and
pcm
- 2022-05-12 11:08:54下载
- 积分：1
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Its-GPS-ranging-codes
GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)
- 2014-03-20 08:51:27下载
- 积分：1
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RTC
verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
- 2009-12-19 23:51:50下载
- 积分：1
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VerilogHDL
本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是Verilog HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。(This book briefly introduces the Verilog hardware description language basics, including basic elements of language and basic structure, and the use of the language at various levels on the digital system modeling. The book lists a large number of examples to help readers master the language itself and the modeling of the actual digital system design is also helpful. Verilog HDL book is a primer for a computer, electronic, electrical and automatic control and other specialized courses related to materials, but also for the researchers as a reference.)
- 2010-05-11 19:54:29下载
- 积分：1
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用VHDL语言设计四位全加器，有低位进位和高位进位。
用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.
- 2022-03-20 15:03:38下载
- 积分：1
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这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用...
这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
- 2022-05-22 23:36:04下载
- 积分：1
