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XDS100v3-Design-Kit-1.0-Setup
压缩包是ti xds100v3 Design kit的安装文件,安装后有原理图、PCB文件,与DSP接口采用FPGA,安装后有源码,是VHDL格式的,支持开源,降低开发成本(Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is VHDL formats, support for open source, reduce development costs)
- 2014-08-28 09:36:34下载
- 积分:1
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基于FPGA,实现了移位除法的功能,程序接口简单,十分好用,已经验证。...
基于FPGA,实现了移位除法的功能,程序接口简单,十分好用,已经验证。-Based on the FPGA, to achieve the division of functional shift, the program interface is simple, very easy to use, has already been verified.
- 2022-10-14 07:10:02下载
- 积分:1
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LDPC_Encoder
verilog 编写的ldpc编码,含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分:1
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用VHDL编写的计算器,能实现简单的加减乘除四则运算
用VHDL编写的计算器,能实现简单的加减乘除四则运算
- 2022-03-18 17:26:25下载
- 积分:1
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以太网总线源代码,里面有详细的文档说明,已经过FPGA验证。...
以太网总线源代码,里面有详细的文档说明,已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.
- 2023-08-25 00:30:05下载
- 积分:1
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TMDXEVM6678L_EVM_A101-1_GBR
TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)
- 2013-08-15 08:50:26下载
- 积分:1
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- 2022-06-02 03:55:25下载
- 积分:1
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时序逻辑与组合逻辑(VHDL)
代码使用应用于 FPGA的VHDL代码,主要是告诉大家时序逻辑和组合逻辑的应用场合和区别,希望能够对大家有所帮助
- 2022-10-19 04:15:03下载
- 积分:1
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完成ITUR656标准的视频流数据向RGB格式的转换。
完成ITUR656标准的视频流数据向RGB格式的转换。-Complete video streaming ITUR656 standard data format to RGB conversion. Test module
- 2022-02-13 16:12:20下载
- 积分:1
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CORDIC_ATAN
使用verilog语言完成了基于cordic算法求反正切的计算,精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)
- 2008-12-24 11:31:00下载
- 积分:1