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turbo_dinter
说明: 电网协议信道解交织器设计FPGA实现,适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)
- 2020-05-08 15:53:18下载
- 积分:1
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class16_pll
说明: FPGA实现PLL锁相环,输出不同频率的时钟控制信号。(FPGA realizes PLL and outputs clock control signals of different frequencies.)
- 2021-03-19 17:19:19下载
- 积分:1
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mun_base
adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz
- 2019-03-28 07:33:03下载
- 积分:1
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UART receiver and transmitter using vhdl
这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出,在接收端进行串行输入和并行输出的算法。
- 2022-02-06 12:51:51下载
- 积分:1
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在利用Verilog在FPGA平台上输出正弦波,实现芯片为Cyclone II 484C8,有管脚分配...
在利用Verilog在FPGA平台上输出正弦波,实现芯片为Cyclone II 484C8,有管脚分配-In the use of Verilog in the FPGA platform, the output sine wave, the realization of the chip for Cyclone II 484C8, has pin allocation
- 2022-01-31 10:21:02下载
- 积分:1
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mu0
基于Xilinx Spartan6的
一个简单的CPU MU0
VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)
- 2020-12-07 08:29:22下载
- 积分:1
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BMD_PCIE
自己根据xapp1052修改的源代码,已经编译成功,并应用在开发板上。(According xapp1052 own modified source code has been successfully compiled and used in the development board.)
- 2015-10-19 08:10:20下载
- 积分:1
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cycle_measure
测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)
- 2013-08-29 16:09:17下载
- 积分:1
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cpu_easy
说明: ADD MOV MOVi SUB四指令cpu设计,qutartus,(Design of four-instruction CPU)
- 2019-05-13 11:44:49下载
- 积分:1
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VHDL
控制电话信令
完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)
- 2010-10-22 20:11:38下载
- 积分:1