-
lut_multiplier
使用verliog设计实现LUT查找表乘法器,通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)
- 2021-04-09 10:18:59下载
- 积分:1
-
rs232_receiver
RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)
- 2009-07-06 19:56:52下载
- 积分:1
-
top
脉冲多普勒雷达回波信号相干积累的VHDL源程序(pulse Doppler radar echo signal coherent accumulation of VHDL source)
- 2021-04-22 20:28:48下载
- 积分:1
-
VHDL、Verilog HDL语言,是华为公司的技术指导书,希望对你有所帮助...
VHDL、Verilog HDL语言,是华为公司的技术指导书,希望对你有所帮助-VHDL、Verilog HDL
- 2022-01-28 23:23:37下载
- 积分:1
-
chuankou_huihuan
FPGA与PC端实现串口数据的收发,先从PC端接收数据,然后发回给电脑,可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)
- 2020-06-16 10:20:01下载
- 积分:1
-
project_first
说明: basys3的数字钟,可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分:1
-
Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP...
Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
- 2022-02-12 19:56:59下载
- 积分:1
-
FPGA_GFP
基于FPGA的GFP(通用成帧协议)封装数据成帧的实现。(FPGA-based GFP (Generic Framing Protocol) encapsulated data Framing realized.)
- 2007-07-20 15:07:59下载
- 积分:1
-
led_test
在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA
)
- 2013-08-13 08:55:45下载
- 积分:1
-
Dac714
dac714的控制程序,包括spi数据通信,转换控制(dac714 control procedures, including the spi data communications, switching control)
- 2011-05-18 09:13:59下载
- 积分:1