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float_mult32x32.v
verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
- 2018-07-19 17:33:42下载
- 积分：1
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用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。...
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
- 2022-10-05 02:20:03下载
- 积分：1
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ANALYSIS-OF-FULL-ADDER
DESCRIPTION OF FULL ADDER
- 2013-11-12 13:32:19下载
- 积分：1
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vhdl+verilog
小波提升算法源码，里面一个txt文件可以当作算法参考；(Wavelet lifting algorithm source code, inside a TXT file can be used as algorithm reference;)
- 2018-06-20 09:28:28下载
- 积分：1
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module_dem
用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现(Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation)
- 2009-10-14 14:47:30下载
- 积分：1
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vhdl语言编程入门实例100个，部分附有仿真波形图，和一些基本的讲解...
vhdl语言编程入门实例100个，部分附有仿真波形图，和一些基本的讲解-vhdl examples
- 2023-07-05 01:10:04下载
- 积分：1
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DAC0832
DAC0832 VHDL源程序 一个适合初学都的程序 (DAC0832 VHDL source code of a program suitable for both beginners)
- 2010-05-07 20:13:47下载
- 积分：1
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the program two integers and the sum of squared output
本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output
- 2023-08-09 04:10:02下载
- 积分：1
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１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用...
１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners
- 2022-03-04 05:06:34下载
- 积分：1
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DDSN
quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真(quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter)
- 2021-03-20 16:49:17下载
- 积分：1
