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Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。...
Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
- 2022-03-21 18:04:20下载
- 积分：1
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FSK
频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
- 2020-09-03 11:28:07下载
- 积分：1
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digital_piano-VHDL
使用VHDL编写数字蜂鸣器音乐，整个项目文件，可直接使用
(Use VHDL to write 1602led driver, the entire project file, and can be used directly.)
- 2020-12-27 22:49:03下载
- 积分：1
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系统设计
说明： 基于旋转编码器和LED灯组的强度调节系统设计(Design of Intensity Regulation System Based on Rotary Encoder and LED Lamp Set)
- 2020-06-21 02:00:01下载
- 积分：1
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iic_sci
FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)
- 2014-12-23 09:32:54下载
- 积分：1
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verilog HDL语言，对于超大规模集成电路开发学习非常有好处
verilog HDL语言，对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning
- 2022-12-28 13:40:09下载
- 积分：1
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10_1_hdmi_test
说明： fpga的hdmi驱动，只包括视频信号没使用音频线，总体跟DVI控制一样，可参考DVI说明手册进行观看(driver of HDMI using fpga)
- 2020-03-01 15:49:44下载
- 积分：1
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CPU
运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)
- 2020-09-21 10:37:53下载
- 积分：1
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本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数
（N+0...
本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数
（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可
通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使
用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
- 2022-08-24 20:51:04下载
- 积分：1
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This code implements the output shift register functions, beginners can learn to...
本代码实现了输出移位寄存器功能，初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn
- 2022-06-20 09:32:02下载
- 积分：1
