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在EFF的代码地址异步FIFO的灰色代码详细设计…
详细设计了异步fifo格雷码中地址码的生效和Man标志的出现
- 2022-02-07 05:32:22下载
- 积分：1
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FPGA
基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
- 2023-01-20 11:30:04下载
- 积分：1
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这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。...
这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。-This procedure is based on the principle of frequency measurement accuracy, such as the frequency meter, using VHDL language, frequency measurement range 1 ~ 9999 with four decimal places with the frequency of the digital display and has a super-range, less range prompts.
- 2022-03-04 13:27:35下载
- 积分：1
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LMS
用verilog编写的lms算法。可实现自适应滤波功能(Lms algorithm written in verilog. Adaptive filtering can be achieved)
- 2021-05-15 11:30:02下载
- 积分：1
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软件开发环境：ISE 7.1i
仿真环境：ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共...
软件开发环境：ISE 7.1i
仿真环境：ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器；
2. 工程在project文件夹中，双击traffic.ise文件打开工程；
3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件；
4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit
- 2022-08-09 15:58:02下载
- 积分：1
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用verilog编写的1024点的fft快速傅立叶变换
用verilog编写的1024点的fft快速傅立叶变换-Verilog prepared using 1024 point fft Fast Fourier Transform
- 2022-05-07 18:57:45下载
- 积分：1
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sphere-decoding-modulation-by-QAM
16QAM,64QAM,256QAM调制下的球形译码(16QAM, 64QAM, 256QAM modulation sphere decoding)
- 2021-03-31 18:29:09下载
- 积分：1
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My_PMSM_SOPC
基于FPGA的PWM波生成程序，用于控制步进电机。(A PWM wave generater for driving stepper motor.)
- 2018-05-07 20:05:05下载
- 积分：1
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FFT_verilog
说明： verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近(verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to)
- 2009-08-26 11:29:57下载
- 积分：1
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DATA_Scramble
扰码器的FPGA实现，选择的扰码器规格为15位移位寄存器。(FPGA scrambler, scrambler specifications for a 15 bit shift register.)
- 2021-01-16 19:28:46下载
- 积分：1
