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my_lms
自适应滤波,对输入信号进行选择性的加权处理,使输出达到最优化,并且能够跟踪和适应系统和环境的动态变化(Least mean square,of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)
- 2010-10-14 15:30:00下载
- 积分:1
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CPU
十一和通过vivado实现多周期cpu,各种作业再里面包含了(Realizing multi period CPU)
- 2020-12-29 10:19:00下载
- 积分:1
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uart
Verilog UART is written in this file
- 2013-04-16 12:34:05下载
- 积分:1
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pld_Tetris
基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行,屏幕倒置,分数显示,vga接口,键盘接口等功能(Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface.)
- 2020-11-06 12:39:49下载
- 积分:1
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sanjose_hdlcon
FFT implementation using C program
- 2014-02-11 21:01:40下载
- 积分:1
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fsk
基于FPGA的fsk调制程序,包括载波的生成,nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)
- 2016-05-12 21:00:56下载
- 积分:1
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IEEE Standard for Verilog 2005
说明: verilog 2005 IEEE 标准手册(IEEE Standard for Verilog 2005 Hardware Description Language)
- 2020-02-10 22:07:05下载
- 积分:1
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简单的CPU(源代码和合成脚本)
应用背景此文件包含所有的源代码和脚本,以Altera公司的简单CPU的合成。500MHz时钟设计运行。 ;关键技术使用CLA提高速度的设计。这只是一个简单的CPU,它的结构很简单,它没有任何管道或类似的东西。
- 2022-04-30 14:14:37下载
- 积分:1
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TDMsystem
实现多路可变时分复用,包括复接器,解复接,比特同步,帧同步,分频器(Implement multi-channel variable time division multiplexing, including multiplexer, demultiplexing, bit synchronization, frame synchronization, frequency divider)
- 2018-09-16 23:29:09下载
- 积分:1
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ba_ker
巴克码装到信息内同时将巴克码识别出来,实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)
- 2014-05-18 17:37:39下载
- 积分:1