登录
首页 » VHDL » High

High

于 2022-07-18 发布 文件大小:44.25 kB
0 98
下载积分: 2 下载次数: 1

代码说明:

高速多通道crc实现,可以并行实现5个通道数据的校验,支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • brazorobotico
    Brazo robotico proyecto para laboratorio
    2015-02-21 05:57:29下载
    积分:1
  • Encoder_SSI_Veryilog
    说明:  本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯(SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementation of the communication with the absolute encoder)
    2020-12-28 20:59:02下载
    积分:1
  • vhdl5
    program for half subtractor.
    2009-10-02 16:10:13下载
    积分:1
  • verilog digital stopwatch to achieve accurate to 10ms
    verilog实现的数字跑表 精确到10ms-verilog digital stopwatch to achieve accurate to 10ms
    2022-04-18 11:51:54下载
    积分:1
  • bubblesort
    根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果,含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)
    2021-05-08 13:28:35下载
    积分:1
  • Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
    Qutuas II v7.1的key_gen 对sp1无效 这就是个v7.1 sp1的key_gen -Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
    2023-07-28 18:25:02下载
    积分:1
  • altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中...
    altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
    2022-12-14 08:55:03下载
    积分:1
  • I2C的VHDL源码,从机模式,编译通过。
    I2C的VHDL源码,从机模式,编译通过。-I2C the VHDL source code, from the mode, the compiler through.
    2023-01-11 08:00:03下载
    积分:1
  • DDR (double rate) SDRAM controller reference design Verilog code, can be directl...
    DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
    2022-11-05 09:15:03下载
    积分:1
  • Clutter-Filtering-
    。给出了时域滤波的基本原理以及通常采用的 IIR 椭圆地物杂波滤波器的设计方法。重点研究了回归滤波器这一时域滤波算 法。从正交多项式的拟合出发,给出了回归滤波器抑制地物杂波的基本原理及 其滤波实现过程。通过对回归滤波器的计算复杂度的研究,寻找使回归滤波器 计算量最小的正交多项式。分析了回归滤波器频率响应特性,比较了回归滤波 器与IIR 椭圆地物杂波滤波器的计算复杂度。利用仿真的雷达信号,分析了回 归滤波器的地物杂波抑制性能。回归滤波器实际上是一高通滤波器,它在滤掉 低频地物杂波的同时,对落在滤波器阻带内的天气回波信号同样会造成衰减。 在天气回波信号谱宽固定的情况下,通过改变天气回波信号的平均多普勒频率, 分析了回归滤波器对它的衰减情况。在基于一组实际采集的雷达信号的基础上, 给出了回归滤波器的地物杂波抑制比随着滤波器阶数的变化情况。(Firstly, this dissertation introduces the research background and significance of ground clutter suppression, analyzes the characteristics of the ground clutter and weather signals in the Doppler weather radars and simulates Doppler radar echo signals (It includes ground clutter, weather echo signals and the mixture of them). The simulated signals are used later to study the time and frequency domain ground clutter suppression. Secondly, this dissertation talks about the time domain filtering, gives the basic theory of time domain filtering and describes the design method of the usually used fifth-order elliptic infinite impulse response (IIR) ground clutter filter. In the time domain, the work focuses on the regression filter. From the orthogonal polynomials fit, this dissertation gives the basic theory of the regression filter for ground clutter suppression and the filtering process using a regression filter. Through the study of the computational complexity of regression)
    2012-07-09 22:12:11下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载