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20190717 - Copy
说明： this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分：1
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通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。
通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。
-Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
- 2022-05-22 23:15:29下载
- 积分：1
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ldpc
最近在做毕设，ldpc码的编解码实现，这个是verilog实现。(Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.)
- 2021-05-14 15:30:02下载
- 积分：1
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This tutorial presents an introduction to Altera’s Nios R
II processor, which...
This tutorial presents an introduction to Altera’s Nios R
II processor, which is a soft processor that can be in-
stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
- 2023-06-21 11:25:02下载
- 积分：1
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VHDLFIR
1 由matlab计算FIR数字滤波器的滤波系数；
2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。
(matlab
VHDL
QUARTUS )
- 2016-05-15 12:49:30下载
- 积分：1
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CPU-Verilog
简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分：1
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通信协议FPGA
说明： 本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8
位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8
Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.)
- 2020-12-11 11:39:19下载
- 积分：1
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FPGA_flash设计
我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)
- 2018-04-21 21:37:17下载
- 积分：1
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基于Xilinx FPGA的OFDM通信系统基带设计
使用ISE软件实现OFDM通信系统的框架搭建，完成上板前的仿真工作(Realization of OFDM communication system with ISE software)
- 2019-03-28 10:21:02下载
- 积分：1
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filter-design
MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)
- 2020-12-02 20:39:26下载
- 积分：1
