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halfband
verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)
- 2020-12-25 14:29:04下载
- 积分：1
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Array-multiplier
Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
- 2015-02-21 12:59:12下载
- 积分：1
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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
- 2022-03-23 18:10:33下载
- 积分：1
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alu
说明： 用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)
- 2009-07-28 16:20:52下载
- 积分：1
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VHDL 乘法器 源代码，很好的VHDL 入门学习例程序
VHDL 乘法器 源代码，很好的VHDL 入门学习例程序-Multiplier VHDL source code, a good learning example VHDL entry procedures
- 2022-05-23 18:46:06下载
- 积分：1
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rtl
SPI verilog RTL code
- 2016-02-29 12:26:08下载
- 积分：1
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vgac_sst160aN
基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机(FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game)
- 2021-04-11 11:18:58下载
- 积分：1
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This document gives the code for programming a CC2500 transceiver using Altera S...
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
- 2022-02-26 15:59:21下载
- 积分：1
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VHDL Checkers Implementation
by
Ibrahim Elbouchikhi
Amir Nader
VHDL Checkers Implementation
by
Ibrahim Elbouchikhi
Amir Nader-Tehrani
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VHDL Checkers Implementation
by
Ibrahim Elbouchikhi
Amir Nader-Tehrani
- 2022-06-13 17:00:51下载
- 积分：1
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niossram
altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板(altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board)
- 2009-04-13 13:26:42下载
- 积分：1
