-
DDS
Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)
- 2015-07-29 19:59:36下载
- 积分：1
-
vga_driver
verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)
- 2016-05-25 17:19:18下载
- 积分：1
-
bhaswatiml
matlab code for communication
- 2013-11-07 00:43:24下载
- 积分：1
-
CPU代码
CPU代码-VHDL语言，实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.
- 2022-02-02 11:14:11下载
- 积分：1
-
HDB3modelsim
HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分：1
-
04432909
基于FPGA实现的神经网络算法ANN。针对手势识别，不错的参考文章。(Hand Postures Recognition System Using Artificial Neural Networks
Implemented in FPGA)
- 2015-06-25 06:34:19下载
- 积分：1
-
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分：1
-
electricwatch
用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)
- 2010-05-07 17:11:53下载
- 积分：1
-
ROM模块，功能在于，是创建一个简易的rom模块
ROM模块，功能在于，是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分：1
-
str
these are verilg prgms
- 2012-12-05 18:12:51下载
- 积分：1
