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FPGA
基于FPGA的电机控制
FPGA-basedMotorControl-FPGA-based motor control FPGA-basedMotorControl
- 2022-04-13 15:15:14下载
- 积分：1
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Features: Based on the VHDL language, realize high
功能：基于VHDL语言，实现对高速A/D器件TLC5510控制-Features: Based on the VHDL language, realize high-speed A/D control devices TLC5510
- 2022-11-12 08:45:02下载
- 积分：1
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mini_cpu_verilog
用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)
- 2011-07-16 09:20:27下载
- 积分：1
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输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2...
输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2-a afdg jhg dfgh r fbnrfer
- 2023-02-24 12:15:03下载
- 积分：1
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4BITMUIT
利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)
- 2013-09-05 10:06:52下载
- 积分：1
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mealy fsm 和moore fsm
mealy fsm å’Œmoore fsm-mealy Fsm and moore Fsm
- 2023-04-04 18:30:04下载
- 积分：1
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Verilog代码支持IO中断的CPU实现
Verilog代码，支持IO，中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)
- 2020-07-05 20:28:59下载
- 积分：1
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3P3_wimdow
图像插值算法，窗口为3*3,用于图像的除去死点，以及提高清晰度或者使图像柔和(3*3 window)
- 2012-02-28 15:36:02下载
- 积分：1
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sim_uart
uart 收发器 verilog 代码，实现自收发功能
sys clk = 25m, baud 9600 停止位1， 无校验位；
代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过；
(verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
- 2010-10-10 21:49:46下载
- 积分：1
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msttr是用vhdl语言开发的一个交通灯程序
msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
- 2022-02-25 21:15:30下载
- 积分：1
