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双电梯控制器
说明: 使用verilog实现的双电梯控制器,1-9层,仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
- 2020-06-17 11:44:27下载
- 积分:1
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基于FPGA的数字钟设计
基于FPGA的数字钟的设计,外部时钟32MHz,通过分频器得到秒脉冲,用于正常工作时的计数脉冲。通过分频还得到一个5ms的脉冲,用于按键的消抖(具体原理可见程序)。输入的信号有三个:1.时钟信号2.校时模式设置按键3.校时调整按键,输出通道6位数码管。共有:校时模块,24计数的小时计数模块,60计数的分钟计数模块,60计数的秒钟计数模块。
- 2022-04-01 05:03:17下载
- 积分:1
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CXFlt
通信系统中的基带信号处理中的成型滤波器代码,已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)
- 2015-03-24 09:43:05下载
- 积分:1
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VHDL example, there are nearly a hundred examples, can be carried out in quartur...
VHDL实例,有近百个实例,都是可以在quarturs 上进行仿真的,大部分都可以通过,对初学者是一非常不错的-VHDL example, there are nearly a hundred examples, can be carried out in quarturs simulation, most of them can pass, for beginners is a very good
- 2022-04-16 23:40:20下载
- 积分:1
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zuse
验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)
- 2017-12-18 17:04:23下载
- 积分:1
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hamid
very nice program that i ensure anyone can use easily and will be efficient for hard project of elevator
- 2009-07-26 13:27:38下载
- 积分:1
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concurrent
VHDL operators basics
- 2013-09-10 14:44:51下载
- 积分:1
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一个完整的viterbi译码程序和测试的程序
一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures
- 2023-01-14 14:40:03下载
- 积分:1
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Cadence_manual_1.2.pdf
Cadence_manual_1.2.pdf
- 2022-01-26 00:20:48下载
- 积分:1
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det
double edfe trigger d latch
- 2014-01-07 19:55:29下载
- 积分:1