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pll
说明： fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:01下载
- 积分：1
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PCM
本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。(This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL language carry out.
)
- 2021-04-23 17:08:47下载
- 积分：1
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In communication systems channel poses an important role. channels can convolve...
In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
- 2022-02-24 17:03:03下载
- 积分：1
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writereadflash
这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)
- 2013-07-14 22:06:38下载
- 积分：1
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I2C
关于I2C总线协议的verilog代码，里面包括了3个verilog代码(I2C bus protocol verilog code, which includes three verilog code)
- 2012-08-31 14:31:29下载
- 积分：1
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VerilogHDL
基于verilog convolutional coding
的卷积编码(verilog convolutional coding
)
- 2012-05-09 22:56:42下载
- 积分：1
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HB1
说明： 半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分：1
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1024-point-FFT-in-verilog.pdf
1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)
- 2014-03-26 22:56:23下载
- 积分：1
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Interpolator-of-polyphase-filter
代码用两种方法设计了一个基于多相滤波的内插器，低通滤波器采用128阶凯撒窗，内插倍数32，并且给定信号范围，验证了内插器的正确性，画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )
- 2021-01-09 13:18:51下载
- 积分：1
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全数字fsk调制解调的实现 verilog源码
全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
- 2023-04-11 15:55:04下载
- 积分：1
