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verilog hdl verilog hdl verilog hdl

于 2022-07-23 发布文件大小:2.04 kB

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verilog hdl verilog hdl verilog hdl-verilog hdl

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Verilog prepared using USB download cable program realize USB protocol and JTAG...
用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine

2022-01-26 07:07:00下载

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Copy
this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

2020-06-21 21:00:02下载

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navigation
Ship navigation project

2014-12-04 18:58:16下载

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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be

2022-03-23 18:10:33下载

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am
基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

2013-10-14 22:14:56下载

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FPGA数字信号处理实现原理及方法代码
说明：本光盘是《数字信号处理FPGA实现》一书的配书光盘，内容包括了书中第二章给出的所有示例以及该书的12个实验完整的工程文件。本光盘根目录下有3个文件夹，分别为dsp48_application,dsp48e_application和DSP_Example。(This CD-ROM is the CD-ROM of the book "FPGA implementation of digital signal processing". It includes all the examples given in Chapter 2 and the complete engineering documents of 12 experiments in the book. There are three folders in the root directory of this CD-ROM, which are dsp48_ application,dsp48e_ Application and DSP_ Example.)

2020-08-01 09:23:20下载

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lab2
说明：使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)

2021-04-23 01:58:48下载

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DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M...
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

2023-07-27 16:00:03下载

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巴克内尔Verilog手册
Bucknell Verilog Manual

2022-02-02 15:04:14下载

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mul
实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

2014-01-12 22:52:38下载

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verilog hdl verilog hdl verilog hdl

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