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可综合的Verilog语法和语义，从大学教师cambri…
《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
- 2022-03-31 07:34:29下载
- 积分：1
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完成的是RS422信号的计数功能，并产生一定的触发信号
完成的是RS422信号的计数功能，并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals
- 2022-04-14 14:08:50下载
- 积分：1
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FPGA-DSP
vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)
- 2021-01-08 10:58:51下载
- 积分：1
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用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。...
用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。-Using VHDL language, and music performance procedures, examples of songs as
- 2022-05-30 16:58:33下载
- 积分：1
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wide_cbf
宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)
- 2013-03-19 09:40:45下载
- 积分：1
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Verilog prepared practical multi
verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table
- 2022-04-23 06:46:24下载
- 积分：1
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使用vhdl语言编写的100个常用程序的例子
使用vhdl语言编写的100个常用程序的例子-The use of VHDL language 100 examples of commonly used procedures
- 2022-08-18 05:39:29下载
- 积分：1
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iic
说明： 通过iic总线实现数据的读和写，以及基于的modelsim测试。(Through the iic bus to achieve data reading and writing,and based on the modelsim test.)
- 2019-10-08 15:04:32下载
- 积分：1
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lab4showTAs
4 seg display, button debouncer, and controller for parking meter
- 2010-11-10 16:17:42下载
- 积分：1
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DAC0832VHDL
DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真(DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL)
- 2020-11-28 12:59:31下载
- 积分：1
