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VHDL
先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分：1
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vhdl经典源代码――vga控制，入门者必须掌握
vhdl经典源代码――vga控制，入门者必须掌握-vhdl classical source code-- vga control, beginners must master
- 2022-03-28 12:21:35下载
- 积分：1
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万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！...
万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
- 2022-01-26 04:43:16下载
- 积分：1
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ofdm_baseband_design_basedon_fpga
基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)
- 2013-06-13 22:13:52下载
- 积分：1
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SimpleSpi
master spi的源代码（verilog），包括文档，测试程序(master spi the source code (verilog), including documentation, testing procedures)
- 2007-01-29 21:03:51下载
- 积分：1
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irda.tar
depends on irda transmitter recever
- 2009-11-20 00:31:48下载
- 积分：1
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VHDL language learning paradigm, the FSK
学习VHDL语言的范例，有关FSK-VHDL language learning paradigm, the FSK
- 2023-06-01 13:25:03下载
- 积分：1
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is61lv25616 (1)
verilog测试，fpga测试片外sramis61lv25616，256个k个字，16位，比较难调(it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .)
- 2020-12-09 15:39:18下载
- 积分：1
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SERDES_handbook
SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)
- 2017-01-12 18:28:41下载
- 积分：1
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FPGA实现 DDS_讲的非常详细,师兄的一片论文
FPGA实现 DDS_讲的非常详细,师兄的一片论文-FPGA realize DDS_ talked about in great detail, of a senior thesis
- 2023-03-01 11:00:04下载
- 积分：1
