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实战训练21 SDRAM硬件控制
说明： SDRAM硬件控制,fpga的verilog语言，适合学习(SDRAM hardware control, Verilog language of FPGA, suitable for learning)
- 2020-04-29 11:45:16下载
- 积分：1
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master_slave
AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
- 2019-03-22 22:24:20下载
- 积分：1
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基于Verilog的PCI总线接口的设计及应用
基于Verilog的PCI总线接口的设计及应用-Verilog-based PCI-bus interface design and application.
- 2023-01-05 03:35:06下载
- 积分：1
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processor
processor design istruction load pipeline ,hazard
- 2010-04-02 03:52:08下载
- 积分：1
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fenpin
这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)
- 2013-11-17 15:01:30下载
- 积分：1
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Verilog prepared using USB download cable program realize USB protocol and JTAG...
用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine
- 2022-01-26 07:07:00下载
- 积分：1
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H.264中二进制算术编码的硬件实现 H_264
H.264中二进制算术编码的硬件实现Binary arithmetic coding in H.264 hardware implementation(Binary arithmetic coding in H.264 hardware implementation)
- 2020-06-28 14:20:02下载
- 积分：1
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VHDL language used to achieve a display hours, minutes and seconds of the clock:...
用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.
- 2022-04-27 22:51:31下载
- 积分：1
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- 2022-12-14 10:50:03下载
- 积分：1
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112
用MSP430进行压力测试，完成数据的分析(with msp430 to continue on press test.to complete about the anlysys about data)
- 2012-08-31 16:10:15下载
- 积分：1
