-
8_sys_clock
黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)
- 2012-09-18 22:51:36下载
- 积分：1
-
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-25 16:18:57下载
- 积分：1
-
testbench(xilinx)
Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生
激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce
Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)
- 2012-04-18 16:08:25下载
- 积分：1
-
paper7
分数阶Unscented卡尔曼滤波器研究.pdf(Fractional Unscented Kalman filter pdf)
- 2012-12-27 21:00:41下载
- 积分：1
-
VHDL language learning paradigm, the FSK
学习VHDL语言的范例，有关FSK-VHDL language learning paradigm, the FSK
- 2023-06-01 13:25:03下载
- 积分：1
-
数字信号处理的FPGA实现(第4版)源码
数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
- 2021-01-16 23:08:50下载
- 积分：1
-
NN-using-FPGA
thesis about design and implementation neural network using FPGA
- 2013-12-29 16:23:52下载
- 积分：1
-
qam_64
64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核(64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS)
- 2021-03-02 23:29:33下载
- 积分：1
-
xilinx 开发板原程序，双口RAM控制
xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
- 2022-07-26 06:17:10下载
- 积分：1
-
Continuous_acoustic_emission_board
多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)
- 2020-06-25 13:00:01下载
- 积分：1
