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Convolution
卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)
- 2017-10-14 19:46:22下载
- 积分：1
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频率计，ＶＥＲＩＬＯＧ代码，含详细 中文注释．
频率计，ＶＥＲＩＬＯＧ代码，含详细 中文注释．-Cymometer, VERILOG code, containing a detailed Chinese Notes.
- 2023-05-22 17:20:02下载
- 积分：1
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serial port simulated programme of lattice
lattice的串口仿真的程序- serial port simulated programme of lattice
- 2023-04-29 09:40:03下载
- 积分：1
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VHDL硬件描述语言与数字逻辑电路设计――
VHDL语言的基本知识和设计逻辑电路的基本方法及NAX的使用...
VHDL硬件描述语言与数字逻辑电路设计――
VHDL语言的基本知识和设计逻辑电路的基本方法及NAX的使用-VHDL hardware description language and digital logic circuit design
- 2022-08-23 07:30:13下载
- 积分：1
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bit
// Data port, granularity 8
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined-//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISH
- 2023-03-16 01:05:04下载
- 积分：1
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i2c
说明： PIC32MX4系列单片机I2C总线模块示例代码
PIC32MX4系列单片机I2C总线模块示例代码PIC32MX4系列单片机I2C总线模块示例代码PIC32MX4系列单片机I2C总线模块示例代码(PIC32MX4 I2C
PIC32MX4 I2C
PIC32MX4 I2C
PIC32MX4 I2C)
- 2011-03-31 09:35:50下载
- 积分：1
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fft64
verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分：1
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JOP字节码获取的源码，很重要，具体FPGA中实现
JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA
- 2022-01-26 02:39:47下载
- 积分：1
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e2
Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
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扰码器的verilog实现,参考802.11a相关标准
扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
- 2022-03-13 09:09:35下载
- 积分：1
