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这是一个FPGA sparttan 3E基础工程，
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.
- 2022-11-15 01:50:04下载
- 积分：1
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基于FPGA的OFDM信号传输系统VHDL源码
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
- 2022-02-13 14:58:13下载
- 积分：1
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N-bits-by-M-bits
这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)
- 2013-10-05 19:44:52下载
- 积分：1
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基于FPGA的多波形发生器
基于FPGA的多波形发生器
基于FPGA的多波形发生器
基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator
- 2022-03-17 22:22:40下载
- 积分：1
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mike11xns
mike11河道断面处理软件，将断面格式写成11要求的格式(MIKE11 river section processing software, the section format 11 format
)
- 2021-04-06 17:29:02下载
- 积分：1
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跑马灯VHDL程序
跑马灯（几个LED灯动态闪烁，产生特定方波信号如01010111要用到单个LED灯，请尝试修改paomadeng程序完成）、数码管显示（例如在三个数码管上显示“sos”）、蜂鸣器、LED点阵显示等程序，现在综合如下，其中xx是按键防抖模块，可以不加。
- 2022-09-03 11:00:03下载
- 积分：1
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流水线乘法器的VHDL实现，希望对你会有用！
流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
- 2023-04-03 22:35:03下载
- 积分：1
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Program to implement convolution through VHDL
Program to implement convolution through VHDL-Program to implement convolution through VHDL...
- 2023-02-08 06:15:02下载
- 积分：1
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File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分：1
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Acoustic-Fingerprinting-master
说明： acousting fingerprint enhancement
- 2019-06-03 21:23:50下载
- 积分：1
