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明德扬科教之Gvim_20170511
说明： FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)
- 2021-04-14 19:58:55下载
- 积分：1
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USB_GPIF-II
fpga模拟两路视频，简单拼接后，经过GPIF II接口传出给cy2014，测试usb的吞吐量(fpga generate two lane video, and transmit them through GPIF II interface. test cy2014)
- 2017-06-02 18:50:04下载
- 积分：1
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ConvolutionWithViterbiDecoding
QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分：1
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05_fifo_test
说明： FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分：1
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赛灵思XC2C256频率计的Verilog实现。mt10t7 7
Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
- 2022-03-26 03:57:37下载
- 积分：1
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VLSIrtl_spi
说明： verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.(Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.)
- 2021-05-13 13:30:02下载
- 积分：1
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GPS
通过UART在FPGA数码管上显示经纬度坐标的代码(By UART displayed on FPGA digital latitude and longitude coordinates of the code)
- 2015-06-22 17:14:37下载
- 积分：1
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n_bit_paralleLoadShiftRegJK
n_bit_paralleLoadShiftRegJK
- 2017-11-17 17:27:49下载
- 积分：1
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8_BUS
说明： BUS documentation and map reffereces
- 2020-06-25 19:40:02下载
- 积分：1
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Use Quartus in LCM display static graphics palace
运用Quartus在LCM中显示静态宫殿图形-Use Quartus in LCM display static graphics palace
- 2023-04-14 02:55:03下载
- 积分：1
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