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基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考...
基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考-FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works
- 2022-04-17 01:07:47下载
- 积分:1
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IMPLEMENTATION OF LCD DISPLAY BOARD
本程序给出了在FPGA板上实现LCD显示的方法。支持的FPGA有APARTAN 3、SPARTAN 3E、VIRTEX 3等
- 2023-07-19 05:25:03下载
- 积分:1
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mp3_player
Altera board
Mp3 project
- 2011-12-27 15:04:02下载
- 积分:1
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zidongmen1
说明: 控制步进电机转动,正反转,旋转角度完美掌握。很好用,亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分:1
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mod 6 计数器
在几乎所有的数字系统,计数器被广泛使用的领域,如频率
- 2022-06-14 15:14:34下载
- 积分:1
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synthesis-bandstop-filters
本例介绍直接合成带阻滤波器的方法,n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop
coupled resonator elliptic filters is presented. Two different
coupling schemes, which both include source–load coupling are
used. The first coupling and routing scheme is the standard folded
structure used in implementing bandpass elliptic filters with
transmission zeros using resonators.)
- 2013-03-12 18:19:01下载
- 积分:1
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基于FPGA的彩色符号设计
a、设计可显示横彩条和纵彩条的VGA彩条信号;
b、设计可显示英语字母的VGA彩条信号;
c、设计可显示移动彩色斑点的VGA彩条信号;
d、设计可实现手动切换a、b、c三个功能.(The design can display VGA color color and color of the longitudinal cross signal.
The design can display the VGA color signal of the English alphabet.
The design can display the VGA color signal of mobile color spots.)
- 2020-11-09 16:29:46下载
- 积分:1
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基于VHDL的UART控制器设计
UART模块的VHDL语言设计(Design of VHDL language based on UART module)
- 2017-11-13 23:56:26下载
- 积分:1
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4:2优先编码器的VHDL代码
4:2优先编码设计中的VHDL来为每个输入分配优先级。在CMOS布局1复用器:还设计了4个
- 2022-02-11 13:12:33下载
- 积分:1
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05_fifo_test
说明: FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分:1