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几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码
几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
- 2023-05-10 01:55:03下载
- 积分：1
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Reed-Solomon-RS-ENCODE-DECODE
支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码(This program is an encoder/decoder for Reed-Solomon codes.)
- 2020-12-31 09:48:58下载
- 积分：1
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liftbd53
db53小波的verilog硬件实现源码(Wavelet db53 Verilog hardware source)
- 2008-06-26 10:42:23下载
- 积分：1
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responder3
说明： 基于VHDL的多路抢答器，用LCD12864进行显示(Multiplex answering device based on VHDL is displayed with LCD12864)
- 2019-06-17 15:29:31下载
- 积分：1
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SDRAM 控制器与仲裁者
SDRAM 控制器的多 CPU 系统的公断人将调度内存访问。
- 2023-07-15 19:45:03下载
- 积分：1
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FPGA-design-and-application
已经正式出版，西安电子科技大学出版社，FPGA设计及应用，作者褚振勇(Has been officially published, Xi' an University of Electronic Science and Technology Publishing House, FPGA design and application, the author Zhezhengyong)
- 2009-06-03 15:57:31下载
- 积分：1
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可综合的vhdl设计特点.pdf
可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf
- 2023-08-19 15:25:03下载
- 积分：1
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This application note explains the process of eveloping and debugging a hardware...
This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.
- 2022-01-23 11:16:04下载
- 积分：1
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本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段
时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸...
本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段
时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的
大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细
描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1；
Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
- 2022-02-28 11:38:34下载
- 积分：1
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HW2+李东方+2019211409
说明： 基于数据通路和控制器的高校简单PPM设计(PPM design based on datapath and controller)
- 2020-11-25 02:19:32下载
- 积分：1
