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vjtag
说明： quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)
- 2020-05-06 09:42:50下载
- 积分：1
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watch
数字钟，简单的数电应用，电子表源程序，常用也使用-watch
- 2022-04-18 14:17:50下载
- 积分：1
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NEW
Verilog投币式手机充电仪
清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger
EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)
- 2020-12-10 16:29:20下载
- 积分：1
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本程序实现任意占空比产生，已经在easyfpga030综合过
本程序实现任意占空比产生，已经在easyfpga030综合过-This procedure generated to achieve an arbitrary duty cycle
- 2022-08-03 13:14:41下载
- 积分：1
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e1framerdeframer
E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)
- 2012-12-07 12:10:06下载
- 积分：1
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一个完整的
一种半加器的算法，是基于VHDL软件仿真。请大家下载参考！-A full-adder algorithm is based on the VHDL software emulation. Please download the reference!
- 2022-04-16 00:29:23下载
- 积分：1
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试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左，然后从左到右逐次点亮，全灭全亮；第二种花样为彩灯两边同时亮一个逐次向...
试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左，然后从左到右逐次点亮，全灭全亮；第二种花样为彩灯两边同时亮一个逐次向中间移动再散开；第三种花样为彩灯两边同时亮两个逐次向中间移动再散开；第四种花样为彩灯两边同时亮三个，然后四亮四灭，四灭四亮，最后一灭一亮。四个花样自动变换，重复以上过程。输入时钟频率为500Hz，灯亮的时间在1―4秒之间，可以自由控制。电路中以“1”代表灯亮，以“0”代表灯灭。-Lantern try to design a controller to control 8 lights. The controller has four kinds of lanterns automatically switch the pattern. The first lantern pattern for right-to-left, and then lit from left to right each time, the whole body light second pattern for a lantern light at the same time on both sides of successive spread to the middle of moving again third pattern for lantern light at the same time on both sides to the middle of two successive re-dispersed mobile fourth pattern for the lantern light at the same time on both sides of the three, then four out four bright, four out four-liang, the last light out. Automatically transform the four patterns, repeat the process above. Input clock frequency of 500Hz, the time for lights between 1-4 seconds, they can con
- 2022-08-19 21:54:46下载
- 积分：1
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基于VHDL+FPGA的DDS信号发生设计，已经通过调式
基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
- 2022-06-28 11:38:23下载
- 积分：1
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Pipeline-2
Pipeline processor verilog components
- 2012-12-21 17:53:18下载
- 积分：1
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自适应均衡器
自适应均衡器
- 2023-05-01 16:30:08下载
- 积分：1
