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atomicops_internals_mips_gcc
Protocol Buffers - Google s data interchange format.
- 2015-10-07 09:49:45下载
- 积分：1
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pipeline_booth_mult_16
用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
- 2020-09-29 18:17:44下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
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endat
endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值(endat 2.2 interface cores, sending commands to the encoder or received the encoder position values)
- 2021-05-12 18:30:02下载
- 积分：1
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减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制...
减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
- 2022-01-28 03:17:59下载
- 积分：1
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sram_test
is61lv25616简单的verilog程序，完成sram读写(is61lv25616 simple verilog program, complete sram read and write)
- 2013-07-18 11:16:50下载
- 积分：1
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IPSO
i have coding for verilogHDL and VHDL. so please i want know that coding..
- 2012-04-24 01:01:07下载
- 积分：1
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URAT 部分VHDL源码 大家多多支持 哈哈
URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha
- 2022-02-20 22:56:56下载
- 积分：1
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Sys-gen
System Generator
- 2020-10-25 16:40:00下载
- 积分：1
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可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。
可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。-FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.
- 2022-03-26 18:10:19下载
- 积分：1
